The invention relates to a method for forming a pattern of a semiconductor device.
Due to rapid distribution of information media such as personal portable equipment and a personal computer equipped with a memory device, the development of processes for manufacturing a highly-integrated semiconductor device that has a high storage capacity, improved reliability, and a fast operating speed for accessing data, has been required.
The speed of the semiconductor device is increased as a critical dimension of a pattern, that is, the size of the pattern, is decreased. In order to improve the integration of the semiconductor device, it is important to control the critical dimension of the pattern in application of a photolithography process.
However, it is difficult to form a line and space (L/S) pattern of less than 40 nm by a single exposure process in the photolithography process using an ArF exposer having a common numerical aperture of less than 1.2. Furthermore, it is more difficult to form an L/S pattern of less than 30 nm even when a high index fluid (HIF) material and a hyper-numerical aperture (hyper-NA) exposer are applied together.
In order to solve the problem of the photolithography process, a double patterning technology (DPT) for improving resolution by lowering a K1 factor in a conventional exposer has been developed.
The DPT comprises i) a double exposure etch technology (DEET) and ii) a spacer patterning technology (SPT), which have been used in a semiconductor device producing process.
The DEET can be applied in a process for forming a multi layer pattern, including a brick wall pattern like a landing plug contact (LPC), a gate, and a bit line. The DEET includes forming a first pattern having twice as large a pitch than a pattern pitch, and forming a second pattern having the same pitch as that of the first pattern between the first patterns, thereby obtaining a pattern having a desired resolution. However, the DEET requires more masks and etching steps for forming the first and second patterns, and causes mis-alignment in the mask process for forming the first and second patterns.
The SPT can be applied in a NAND process including a large amount of metal layers and control gates each consisting of a line and space. Since a mask process for forming a pattern is performed once in the SPT, the SPT is a self-alignment technology for preventing mis-alignment of the mask process. However, the SPT requires a patterning process for cutting a spacer pattern portion and a patterning process for forming a pad pattern in a mat edge portion.
FIGS. 1a to 1d are diagrams illustrating a conventional spacer patterning technology.
Referring to FIG. 1a, a deposition structure including a first mask film 15 and a second mask pattern 17 is formed by a photolithography process over an underlying layer 13 of a substrate 11.
Referring to FIG. 1b, an insulating film 19 is formed over the resulting structure including the second mask pattern 17.
Referring to FIG. 1c, an etch-back process is performed to anisotropically-etch the insulating film 19, thereby forming an isolated spacer 19-1 at sidewalls of the second mask pattern 17.
Referring to FIG. 1d, the second mask pattern 17 is removed to form a horn-type spacer pattern 19-2.
Since the spacer pattern 19-2 has an asymmetrical shape, when the lower underlying layer 13 is etched using the spacer pattern 19-2 as an etching mask a pattern having low critical dimension uniformity is formed, as shown in FIG. 2. As a result, the reliability of the semiconductor device is reduced, and the yield of the semiconductor device is decreased.